The present invention relates to a period measuring circuit, and more particularly to a period measuring circuit using a timer.
FIG. 1 is a block diagram illustrative of a conventional period measuring circuit. The conventional period measuring circuit has an external trigger signal input terminal 101 to which an input trigger signal S1 is inputted. The conventional period measuring circuit also has a period measuring circuit section 102 which is connected to the external trigger signal input terminal 101 for receipt of the input trigger signal S1. The period measuring circuit section 102 is also configured to receive a timer count clock signal T1 so that the period measuring circuit section 102 is operated in accordance with the timer count clock signal T1. The conventional period measuring circuit also has a central processing unit 100 which is connected to the period measuring circuit section 102 for receiving informations from the period measuring circuit section 102 and also sends control signals S2 to the period measuring circuit section 102 for control of operations of the period measuring circuit section 102.
FIG. 2 is a block diagram illustrative of a conventional period measuring circuit section in the conventional period measuring circuit of FIG. 1. The period measuring circuit section 102 has a timer 103 which receives the timer count clock signal T1 for performing the counting operation in n-bit length (n.gtoreq.1) based upon the timer count clock signal T1. The timer 103 is also connected to the central processing unit 100. The timer 103 has a predetermined counting capability. If a value counted by the timer 103 exceeds the predetermined counting capability, then the timer 103 outputs a timer overflow signal S3 which will be transmitted to the central processing unit 100 so as to notify the central processing unit 100 of the overflow. The period measuring circuit section 102 also has an edge detection circuit 109 which is connected to the external trigger signal input terminal 101 for receipt of the input trigger signal S1 so as to detect a rising edge of the input trigger signal S1 or a falling edge thereof or both rising and falling edges of the input trigger signal S1. The edge detection circuit 109 outputs an edge detection signal. The period measuring circuit section 102 also has a capture register 104 which is connected to the edge detection circuit 109 for receipt of the edge detection signal from the edge detection circuit 109 as a trigger signal for the following capturing operation. Further, the capture register 104 is of an m-bit length (m.gtoreq.1). The capture register 104 is also connected to the timer 103 for capturing the currently counted value by the timer 103 in accordance with the edge detection signal having been received as a trigger signal from the edge detection circuit 109. The period measuring circuit section 102 also has a first random access memory 105 of x-bits (x.gtoreq.1) which is connected to the capture register 104 for receiving the currently counted value from the capture register 104 to store the currently counted value therein until the capture register 104 captures the next counted value from the timer 103 upon receipt of the next trigger signal of the edge detection signal from the edge detection circuit 109. The period measuring circuit section 102 also has a second random access memory 106 of y-bits (y.gtoreq.1) which is connected to the first random access memory 105 for receiving the previously counted value from the first random access memory 105 to store the previously counted value therein until the capture register 104 captures the next counted value from the timer 103 upon receipt of the next trigger signal of the edge detection signal from the edge detection circuit 109. The above first and second random access memories 105 and 106 are connected to the central processing unit 100 for allowing the central processing unit 100 to fetch the currently counted value from the first random access memory 105 and also fetch the previously counted value from the second random memory 106 for subsequent subtraction operation of the previously counted value from the currently counted value. The period measuring circuit section 102 also has a third random access memory 107 of z-bits (z.gtoreq.1) which is connected to the central processing unit 100 for storing the subtraction result form the central processing unit 100.
FIG. 3 is a flow chart illustrative of operations of the conventional period measuring circuit of FIG. 1. With reference to FIG. 3, the operations of the above conventional period measuring circuit will be described as follows.
In a first step S101, the edge detection circuit 109 monitors the input signal S1 having been inputted to the external trigger signal input terminal 101 in order to detect a predetermined waveform pulse signal, for example, a rising edge, a falling edge or both.
In the second step S102, if the edge detection circuit 109 confirms the input of the predetermined waveform pulse signal, then the edge detection circuit 109 sends an edge detection signal as a trigger signal to the capture register 104, whereby the capture register 104 captures the currently counted value counted by the timer 103 in accordance with the edge detection signal having been received as a trigger signal from the edge detection circuit 109. The central processing unit 100 transfers the currently counted value having now been captured by the capture register 104 to the first random access memory 105.
In the third step S103, the central processing unit 100 transfers the previously counted value from the first random access memory 105 to the second random access memory 106, wherein the previously counted value had been counted by the timer 103 in the previous counting operation thereof and then stored in the first random access memory 105 until the currently counted value has been counted by the timer 103 in the present counting operation and having been now transferred through the capture register 104 to the first random access memory 105. The central processing unit 100 performs a subtraction operation to subtract the previously counted value stored in the second random access memory 106 from the currently counted value stored in the first random access memory 105.
In the fourth step S104, the central processing unit 100 confirms continuously whether or not the over-flow signal S3 has been received from the timer 103 so as to confirm whether or not the timer 103 is in over-flow state.
In the fifth step S105, if the over-flow state of the timer 103 was confirmed by the central processing unit 100, then the central processing unit 100 sends an instruction to the period measuring circuit section 102 to discontinue the currently executed frequency measurement operation. This currently executed program enters another routine. The contents to be executed in the other routine depend upon the contents of the device or apparatus for which the period measuring circuit is utilized, but are independent from the operations of the period measuring circuit.
In the sixth step S106, if no over-flow state of the timer 103 could be confirmed by the central processing unit 100, then the central processing unit 100 sends the subtraction result obtained in the above third step S103 to the third random access memory 107 whereby the third random access memory 107 stores the subtraction result.
In the seventh step S107, the central processing unit 100 writes the counted value stored in the first random access memory 105 to the second random access memory 106 as the previously counted value.
After the seventh step S107, the operation of the period measuring circuit will be back to the above first step S101 so that the edge detection circuit 109 monitors the input signal S1 having been inputted to the external trigger signal input terminal 101 in order to detect the predetermined waveform pulse signal, for example, the rising edge, the falling edge or both.
The above period measuring circuit has the following problems. In accordance with the above conventional period measuring circuit, even when the edge detection circuit 109 could detect the predetermined waveform pulse signal, for example, the rising edge, the falling edge or both, then the period measuring operation will be made during which the central processing unit 100 operates measuring the frequency. This means that every time the edge detection circuit 109 detects the predetermined waveform pulse signal, for example, the rising edge, the falling edge or both, then the central processing unit 100 is shared and becomes engaged with the period measuring operations.
It is further necessary for the above conventional period measuring circuit that the central processing unit 100 also operates to selectively remove shorter-frequency signals than the measuring frequency range from the inputted signals having been inputted to the external trigger signal input terminal 101.
Furthermore, it is difficult to judge from the capture value whether or not the over-flow of the timer 103 has appeared, for which reason the central processing unit 100 is also required to refer over-flow bits in order to confirm whether the timer 103 is in the over-flow state.
From the above descriptions, it can be understood that the burden upon the central processing unit 100 is heavy.
In the above circumstances, it had been required to develop a novel period measuring circuit free from the above problems and disadvantages.